1. Field of the Invention
The present invention relates generally to circuit boards and packages in communication systems, and in particular to structures and methods for routing over a void for high speed signal routing in communication systems.
2. Background Art
Data transmission speed requirements have dramatically increased over recent years. Electronic systems typically use printed circuit boards and/or packages that are interconnected to produce various functionalities of the data transmission process. Each printed circuit board or package contains one or more layers upon which components are placed. Connectivity between the components proceeds by way of conductive paths that are commonly referred to as metal traces, or just traces. Traces are formed on a number of metal layers that form a part of the printed circuit boards and/or packages. In high speed circuit design, the most commonly used transmission lines for these traces are microstrip and stripline. Both of these transmission lines require a uniform reference plane to ensure the integrity of the signals that propagate along the transmission lines.
In high density interconnect situations, a large number of circuit layers are required to provide the desired large number of connections. In such situations, the circuit board or package often contains a rigid core layer so as to provide the required stability and rigidity. Thin layers that form the desired circuit layers are applied on one or both sides of the rigid core layer in order to provide the required stack-up of the circuit board or package to meet the interconnect requirements.
Vias (or plated through holes) provide electrical (and at times thermal) connectivity between the layers of a printed circuit board or package. Vias can be of different size diameters based on factors such as the interlayer distance involved. For example, a via that passes through the thick core of the printed circuit or package is larger in diameter than another via that passes from one thin circuit layer to its adjacent thin circuit layer.
Thick core vias provide transmission of signal, ground or power through the core in the circuit board or package. However, the use of vias results in voids on reference planes used for the transmission lines. For example, the anti-pad associated with a via will cause a void. An antipad is an absence of metal on a layer in the vicinity of the via. In the two metal layers that are disposed just above and below the core layer, there are typically numerous big voids due to the large anti-pad size requirements of the thick vias passing through the core layer.
As a consequence, practical circuit board and package design must deal with imperfections such as the voids that result from the presence of antipads associated with vias. In the case of a void in a reference plane, the void disrupts the uniformity of a reference plane, and therefore transmission lines that are routed over a void (“routing-over-void”) are degraded in performance. For example, the presence of via antipads results in a change to the impedance of a signal trace in the immediate vicinity of the void. Impedance changes of transmission lines result in reflections, degradation in signal trace propagation performance and can, under certain circumstances, result in interconnection failures.
Increased data transmission speed requirements and the need for reduced circuit board size and reduced package size place an emphasis improving the density of trace routing within the circuit board or package. Smaller circuit board size and smaller package size requires maximization of the utilization of all available real estate on the circuit layers of the printed circuit board and package.
Current design practice dictates that traces not be routed in the area below or above a void in order to eliminate the signal propagation degradation associated with the void. However, such a design practice reduces routing density and therefore leads to an increase in the number of stack-up layers and/or increased circuit board/package dimension. Such increases in turn result in an undesired increase in product cost.